We are facing challenging new developments in Chip-Package-System (CPS) design. Whereas Chip design has been driven by Moore’s law for over 50 years, Package and System (board) design traditionally has evolved at a more sedate pace. However, packaging is emerging as a major way to provide adaptability for speed and density while reducing power and form factor, and technology has reached a state, which poses new challenges for Package and System design. Unlike Moore’s Law this has to do less with the geometric complexity – such systems can be represented with tens- to hundreds-of-thousand elements – but more with the analysis: it is increasingly necessary to calculate the complex electromagnetic fields to be able to model them accurately. We call this electromagnetic integrity.
Packaging technology is a good proxy to explain the challenges of CPS design. Packages provide electrical connections for signal, power and ground between the chip and the system (board), as well as means of thermal dissipation and mechanical protection (we do not address the latter two in this paper). Packaging can be a limiting factor in both cost and performance of an electronic product. Increased markets for certain electronic products obviously drive demand for CPS. For example, the explosive growth of mobile devices such as smartphones (about 33% in 2011), and tablets (more than 300% in 2011) has been a strong driver of demand. These two system applications alone have demands on the board designer to decrease area to accommodate the increased displays and battery sizes in spite of continued system complexity increases.
The ITRS Roadmap for Assembly and Packaging [ITRS09] states that one of the difficult challenges is “coordinated design tools to address chip-package-substrate-system co-design”, in particular:
- Rapid turn-around for modeling and simulation
- Power/signal integrity/disturbs, Electromagnetic Interference, higher frequency, lower voltage
- Modeling of 3D structures, Through Silicon Vias (TSV)
- 3D tools for System in Package (SiP)
The main technology drivers which impact electromagnetic integrity are listed below. The trend figures given are from [ITRS09].
Higher frequencies: In the next ten years, the frequency from Chip to Board is expected to double for memory from 1.6 to 3.2GHz. Ten years ago this was the domain of microwave and military applications. Today for mobile applications it will stay around 1GHz; for high-performance systems high-speed serial links are expected to rise from 12Gb/s to perhaps 60Gb/s. Why is it a problem now? Frequencies around 100Mhz with a wavelength of 3 meters require little or no electromagnetic integrity analysis. However for systems running at 1GHz with fast clock transition times there is a significant amount of energy above 10GHz; the wavelength at 10GHz is only 3cm (typically 1.5cm with dielectric) and electromagnetic analysis is a must. Inductance, signal and power loss, resonances, and isolation also become major effects at higher frequencies and to extract them accurately it is necessary to solve the electromagnetic fields and ensure electromagnetic integrity.
Decreasing Voltage: Voltage will decrease only slightly from typically 0.5-1V today to 0.4-0.8V in the next ten years. Low voltages mean progressively smaller margins for device switching and higher susceptibility to noise. They require careful power integrity analysis, which in turn requires electromagnetic integrity.
Increasing Density: In the next ten years, high-performance packages will double their pin count to about 9000; substrates will reduce line width and spacing by about 50% to 20-30m for PBGA and FBGA, 5m for SiP and Package on Package (PoP); through-substrate vias and package ball pitches will remain at 200-300m; TSV pitches are expected to be between 1-40m. Wafer Level Chip Scale Packages with BGA pitches of 100-200m are increasingly common. The density overall is expected to increase slightly, but this means increase electromagnetic coupling and interference at every net and pin. Referencing (localized current return paths) is also likely to become poorer creating more common mode current and more radiation, which leads to a degradation of electromagnetic integrity.
3D Integrated Circuit Packaging (3DIC): As shown in the Figure above, several 3D techniques are being developed, such as mounting ICs on a Silicon Interposer, Stacked Dies and Package on Package (PoP). Through Silicon Vias (TSVs) are used to connect the different levels in several of these technologies. These 3D structures are large compared to a chip and need to be modeled accurately electromagnetically. For example, modeling a TSV in a high-density, high-frequency application, accounting for all interactions, requires an electromagnetic field solver.
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